AD converters are devices for outputting a digital code according to a sampled analogue input voltage. There are various architectures for AD converters, and the architecture is selected according to requirements such as conversion speed and resolution determined according to the application.
As a successive approximation-type AD converter, a form of AD converter, a known converter includes a capacitor DA converter and a comparator. The capacitor DA converter includes a capacitor array including plural capacitors with binary-weighted capacitance values. In a successive approximation-type AD converter equipped with a capacitor DA converter, the magnitude relationship between a reference voltage generated by the capacitor DA converter and an analogue input voltage is determined plural times using the comparator, and a digital code is output according to the determination results.
As structures of a capacitor formed in a semiconductor integrated circuit, known structures include a parallel plate structure and a comb structure.
There is, for example, a proposal for a semiconductor device including a capacitor element, a shield body potential-fixed at a specific electrical potential, and plural wiring layers stacked in multiple layers on a semiconductor substrate, with insulation films interposed between each adjacent layer. In such a semiconductor device, the capacitor elements include a first electrode and a second electrode formed in a first wiring layer out of plural wiring layers, on either side of an insulating layer. A shield body includes a first conductor formed so as to surround the capacitor elements in the first wiring layer in plan view, and a second conductor formed so as to, in plan view, surround the capacitor elements in a second wiring layer that is a layer in the plural wiring layers above the first wiring layer.
A semiconductor device is also proposed including a semiconductor substrate, capacitor elements each including a lower electrode formed above the semiconductor substrate, a capacitor insulation film formed above the lower electrode, and an upper electrode formed above the capacitor insulation film, and a shield layer formed above or below the capacitor elements. This semiconductor device includes a lead-out wiring layer, electrically connected to the lower electrode or the upper electrode, and formed between the capacitor elements and the shield layer, with plural holes formed in both the shield layer and the lead-out wiring layer.
There is also a proposal for a semiconductor integrated circuit including plural capacitor cells each including a first electrode and a second electrode, a first wiring line connected to the first electrode and a second wiring line connected to the second electrode, and a shield wiring line provided so as to suppress capacitance coupling between the first wiring line and the second wiring line.